1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a technique capable of attaining both high-speed access and low current consumption in an inactive state.
2. Description of Related Art
As the digital system becomes more and more high in its function, both large memory storage and high speed of data access are being required of a semiconductor memory device.
For the speed-up of data access it is necessary to attain the speed-up of a sense amplifier which amplifies read memory cell data. To this end it is necessary to improve the drivability of a driver which supplies electric power to the sense amplifier. The sense amplifier is constructed so as to be supplied with electric power and activated at the time of performing an amplifying operation and not supplied with electric power in an inactive state thereof. The driver is provided with a driver-dedicated MOS transistor which provides a connection between the sense amplifier and a power supply, and it turns conductive in the amplifying operation to supply electric power to the sense amplifier. Improving the drivability for ensuring as sufficient supply of electric power to the sense amplifier means decreasing ON-resistance while the driver is conductive. Therefore, it is necessary to use a driver-dedicated MOS transistor having a sufficient gate width W and sufficient current drivability. Further, it is necessary to ensure a sufficient wiring region for the driver-dedicated MOS transistor.
With an increase of capacity, the number of sense amplifiers used increases, resulting in that the layout region of a group of sense amplifiers supplied with electric power from one driver-dedicated MOS transistor becomes very wide and a positional relation between the driver-dedicated MOS transistor and the sense amplifiers differs greatly sense amplifier by sense amplifier. For ensuring a high-speed performance of the sense amplifier located at the remotest point it is necessary to use a driver-dedicated MOS transistor having a large gate width W.
In view of the above-mentioned circumstances there heretofore has been proposed a dispersive layout of driver-dedicated MOS transistors in which driver-dedicated MOS transistors are embedded dispersively in a sense amplifier layout region so that each driver-dedicated MOS transistor is allocated to a predetermined number of sense amplifiers. This method attempts to secure a gate width W having sufficient current drivability and the speed-up of access while minimizing an increase in the layout area of driver-dedicated MOS transistors.
Recently, portable devices which realize high function digital systems have become popular. In a portable device, for improving a continuous operation time characteristic in battery drive, it is absolutely necessary to decrease the power consumption in a stand-by state. In a stand-by state it is absolutely necessary to decrease the leakage current of MOS transistors, etc.
As a typical leakage current in MOS transistor, a drain current is conceivable which is known as a so-called sub-threshold characteristic (tailing characteristic) and which flows when the gate-source voltage bias is below the threshold voltage. With a lowering of the threshold voltage, the sub-threshold characteristic (tailing characteristic) becomes more and more conspicuous. If a comparison is made in terms of a predetermined voltage bias of below the threshold voltage, the lower the threshold voltage,the more flows the drain current. If the threshold voltage lowers to below 0.4V or so, it becomes impossible to completely cut off the drain current even with no voltage bias applied between the gate and the source. The drain current in this state is particularly called tailing current.
However, the conventional dispersive layout method intends to ensure sufficient current drivability and high-speed access while minimizing an increase of the layout area of driver-dedicated MOS transistors, so that the overall gate width W of driver-dedicated MOS transistors becomes large. In addition, a source terminal is connected to a power supply and a large voltage is applied between the drain and the source. Coupled with these points, at a low threshold voltage there flows much tailing current, thus giving rise to the problem that it is impossible to attain a low current consumption in a stand-by state.
Further, ensuring sufficient current supply capability of a driver-dedicated MOS transistor which is necessary for the speed-up of data access and decreasing the tailing current of a driver-dedicated MOS transistor which is necessary for attaining a low current consumption in a stand-by state, are in a trade-off relation. Therefore, in the field of portable devices having a high-function digital system, it is important to adjust both characteristics. In the prior art, however, it is impossible to make an adjustment for the simultaneous attainment of both ensuring sufficient current drivability of a driver-dedicated MOS transistor and decreasing the tailing current, such as the adjustment of transistor size, adjustment of voltage bias condition, and adjustment of threshold voltage. This arises a problem in mounting a high-function digital system in a portable device.
The present invention has been accomplished for solving the above-mentioned problems and it is an object of the invention to provide a semiconductor memory device having a driver transistor for the supply of electric power and capable of diminishing leakage current in an inactive state while ensuring sufficient power supply capability for a sense amplifier in an inactive state.
For achieving the above-mentioned object, according to first aspect of the present invention, there is provided a semiconductor memory device comprising: at least one sense amplifier disposed in at least one sense amplifier layout region correspondingly to a wiring pitch of bit lines; and at least one driver-dedicated MOS transistor for the supply of electric power to the sense amplifier, the driver-dedicated MOS transistor being disposed in the sense amplifier layout region in such a manner that its gate width is oriented perpendicularly to the wiring direction of the bit lines, wherein a power terminal of the sense amplifier and a drain terminal of the driver-dedicated MOS transistor are connected with each other through a low resistance wiring layer.
In the semiconductor memory device according to the first aspect, the driver-dedicated MOS transistor is disposed in the sense amplifier layout region where the sense amplifier is disposed, in such a manner that its gate width direction is perpendicular to the wiring direction of bit lines, and electric power is fed from the drain terminal of the driver-dedicated MOS transistor to the power terminal of the sense amplifier through a low resistance wiring layer.
For the supply of electric power to the sense amplifier with sufficient power supply capability, the driver-dedicated MOS transistor usually has a short gate length and a long gate width. With a long gate width, the gate width can be adjusted freely without being restricted by the wiring pitch of bit lines in a direction perpendicular to the wiring direction of bit lines in the sense amplifier layout region, and it becomes possible to provide a sufficient gate width. As to the gate length, the size of a standard gate length itself is a very small length and hence a sufficient adjustment can be made in an adjustment region of a very small length. Also in a direction parallel to the bit line wiring direction in which the adjustment region is restricted due to a layout restriction of adjacent elements in the sense amplifier layout region, it becomes possible to provide such a gate length as ensures a sufficient adjustment region. Both gate width and gate length can be adjusted with a sufficient degree of freedom and it becomes possible to provide a driver-dedicated MOS transistor of a size adjusted appropriately with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and decreasing the tailing current.
Besides, since the drain terminal of the driver-dedicated MOS transistor and the power terminal of the sense amplifier, both defining a power supply path from the driver-dedicated MOS transistor to the sense amplifier, are connected together by a low resistance wiring layer such as a metal wiring layer, a voltage drop in the wiring path is very small. Also in the case where a single driver-dedicated MOS transistor is connected to a larger number of sense amplifiers, a voltage drop on the power supply path between adjacent sense amplifiers becomes uniform and there is obtained a well-balanced power supply capability for the sense amplifiers.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: at least one sense amplifier disposed in at least one sense amplifier layout region correspondingly to a wiring pitch of bit lines; and at least one driver-dedicated MOS transistor for the supply of electric power to the sense amplifier, the driver-dedicated MOS transistor being disposed in the sense amplifier layout region in such a manner that its gate width is oriented perpendicularly to the wiring direction of the bit lines, wherein a power terminal of the sense amplifier and a drain terminal of the driver-dedicated MOS transistor are directly connected with each other by a constituent layer of both the terminals, and an auxiliary path is formed in at least a partial region by a low resistance wiring layer.
In the semiconductor memory device according to the second aspect of the present invention, the driver-dedicated MOS transistor is disposed in the sense amplifier layout region where the sense amplifier is disposed, in such a manner that its gate width direction is perpendicular to the wiring direction of bit lines, and electric power is fed from the drain terminal of the driver-dedicated MOS transistor to the power terminal of the sense amplifier through a wiring path formed by the constituent layer of both terminals and further through an auxiliary path formed concurrently in at least a partial region by a low resistance wiring layer.
According to this construction, as in the first aspect, both gate width and gate length of the driver-dedicated MOS transistor can be adjusted with a sufficient degree of freedom and it becomes possible to provide a driver-dedicated MOS transistor of an appropriately adjusted size with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and decreasing the tailing current.
Moreover, the drain terminal of the driver-dedicated MOS transistor and the power terminal of the sense amplifier can be connected together at a short distance, thus permitting compression of the layout region, and because of such a short-distance wiring it is possible to suppress a voltage drop in the power supply path from the driver-dedicated MOS transistor to the sense amplifier. There concurrently is formed an auxiliary path by a low resistance wiring layer such as a metal wiring layer, so that the load in the power supply path is further diminished and variations in operation between adjacent sense amplifiers are diminished.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising: at least one sense amplifier disposed in at least one sense amplifier layout region correspondingly to a wiring pitch of bit lines; and at least one driver-dedicated MOS transistor for the supply of electric power to the sense amplifier, the driver-dedicated MOS transistor being disposed in the sense amplifier layout region in such a manner that its gate width is oriented perpendicularly to the wiring direction of the bit lines, wherein the driver-dedicated MOS transistor has a gate length adjustable region between source and drain terminals thereof, the gate length adjustable region permitting a gate layer to be disposed therein which gate layer has a gate length larger than a shortest length value.
In the semiconductor memory device according to the third aspect of the present invention, the driver-dedicated MOS transistor is disposed in the sense amplifier layout region where the sense amplifier is disposed, in such a manner that its gate width is oriented perpendicularly to the wiring direction of bit lines, and the source and drain terminals of the driver-dedicated MOS transistor are arranged while ensuring a gate length adjustable region.
According to this construction, as in the first aspect, both gate width and gate length of the driver-dedicated MOS transistor can be adjusted with a sufficient degree of freedom and it becomes possible to provide a driver-dedicated MOS transistor of an appropriately adjusted size with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and decreasing the tailing current.
Besides, since the driver-dedicated MOS transistor is beforehand provided with the gate length adjustable region, the gate length can be increased and decreased by only adjustment of the gate layer. Thus, in the fabrication of the semiconductor memory device, both current supply capability and tailing current in the driver-dedicated MOS transistor can be adjusted by the correction of only a photomask of the gate layer, and thus it is possible to reduce the adjusting time and cost.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising: a multitude of sense amplifier blocks, the sense amplifier blocks each having in one and same region a predetermined number of sense amplifiers and a driver-dedicated MOS transistor for the supply of electric power to the predetermined number of the sense amplifiers; and a low resistance wiring layer for connecting between the sense amplifier blocks by connecting between power terminals of the predetermined number of the sense amplifiers or connecting between a power output terminal and other power output terminal of respective driver-dedicated MOS transistors in the sense amplifier blocks.
In the semiconductor memory device according to the fourth aspect of the present invention, there are constituted sense amplifier blocks each having in one and same region a driver-dedicated MOS transistor for each predetermined number of sense amplifiers, and power terminals of the predetermined number of sense amplifiers or power output terminal of the driver-dedicated MOS transistor in the sense amplifier block are connected between the sense amplifier blocks by a low resistance wiring layer.
According to this construction, even if the driver-dedicated MOS transistor in a certain sense amplifier block is separated from the predetermined number of sense amplifiers in the same block, electric power is fed thereto from the driver-dedicated MOS transistor in the sense amplifier block adjacent thereto, so that by adjusting connection and non-connection of each individual driver-dedicated MOS transistor it becomes possible to make an appropriate adjustment with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and decreasing the tailing current.
Besides, since connection or non-connection of each individual driver-dedicated MOS transistor can be made depending on whether a contact layer or a low resistance wiring layer is to be laid or not, the adjustment of both current supply capability and tailing current in the driver-dedicated MOS transistor can be made by the correction of a photomask of only one of the contact layer and the low resistance wiring layer, whereby the adjusting time and cost can be reduced.
According to a fifth aspect of the present invention, there is provided a semiconductor memory device including at least one driver-dedicated MOS transistor for the supply of electric power to at least one sense amplifier, wherein in an inactive state not involving an access operation, a difference in applied voltage at a gate terminal relative to a source terminal of the driver-dedicated MOS transistor is reverse-biased relative to a voltage difference in a conductive state.
According to this construction, the driver-dedicated MOS transistor can be reverse-biased more deeply and it is possible to suppress the tailing current while affording a large gate width and a high current drivability. Even in the case where the gate width and length of the driver-dedicated MOS transistor cannot be adjusted to a satisfactory extent, it is possible to make adjustment for ensuring sufficient current drivability and decreasing the tailing current.
According to a sixth aspect of the present invention, there is provided a semiconductor memory device including at least one driver-dedicated MOS transistor for the supply of electric power to at least one sense amplifier, wherein in an active state of the sense amplifier, a difference in applied voltage at a gate terminal relative to a source terminal of the driver-dedicated MOS transistor is forward-biased more deeply than a voltage difference in a conductive state.
According to this construction, the driver-dedicated MOS transistor can be forward-biased more deeply and a higher current drivability can be achieved at a smaller gate width while suppressing the tailing current. Even when the adjustment of gate width and length of the driver-dedicated MOS transistor cannot be made to a satisfactory extent, it is possible to make adjustment for ensuring sufficient current drivability and diminishing the tailing current.
According to a seventh aspect of the present invention, there is provided a semiconductor memory device including driver-dedicated MOS transistor for the supply of electric power to a sense amplifier, the driver-dedicated MOS transistor being deeper in threshold voltage than a sense amplifier-dedicated MOS transistor which constitutes the sense amplifier.
According to this construction it is possible to suppress the tailing current in the driver-dedicated MOS transistor, and even when the adjustment of gate width and length of the driver-dedicated MOS transistor cannot be made to a satisfactory extent, it is possible to make adjustment for ensuring sufficient current drivability and diminishing the tailing current.